void Clock_init()
{
P5SEL |= BIT2+BIT3; // Port select XT2
P5SEL |= BIT4+BIT5; // Port select XT1
SetVcoreUp (0x01); //
SetVcoreUp (0x02);
SetVcoreUp (0x03);
UCSCTL6 &= ~(XT2OFF + XT1OFF); // 开启 XT2 XT1
UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL3 = SELREF__XT2CLK + FLLREFDIV__4; // FLL参考时钟选择
UCSCTL1 = DCORSEL_7; // Select DCO range 50MHz operation
UCSCTL2 = FLLD__1 + 24; // Set DCO Multiplier for 25MHz
// (N + 1) * FLLRef = Fdco
// (24+ 1) * 1MHz = 25MHz
__bic_SR_register(SCG0); // Enable the FLL control loop
{
P5SEL |= BIT2+BIT3; // Port select XT2
P5SEL |= BIT4+BIT5; // Port select XT1
SetVcoreUp (0x01); //
SetVcoreUp (0x02);
SetVcoreUp (0x03);
UCSCTL6 &= ~(XT2OFF + XT1OFF); // 开启 XT2 XT1
UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL3 = SELREF__XT2CLK + FLLREFDIV__4; // FLL参考时钟选择
UCSCTL1 = DCORSEL_7; // Select DCO range 50MHz operation
UCSCTL2 = FLLD__1 + 24; // Set DCO Multiplier for 25MHz
// (N + 1) * FLLRef = Fdco
// (24+ 1) * 1MHz = 25MHz
__bic_SR_register(SCG0); // Enable the FLL control loop